AutoAssert-RV: Automatically Generating Hardware Formal Verification Assertions Using Large Language Models

AutoAssert-RV is an innovative research project that uses Large Language Models (LLMs) to automatically generate formal verification assertions from RTL hardware designs. It aims to address the bottlenecks of time-consuming and error-prone manual assertion writing in traditional hardware security verification, improve verification efficiency and coverage, and provide an AI-assisted solution for the security of hardware designs.

In modern chip design, hardware security verification is crucial yet time-consuming. Traditional formal verification requires engineers to manually write SystemVerilog Assertions (SVA), which demands in-depth understanding of design and verification languages. The exponential growth in chip complexity makes it increasingly difficult to write comprehensive assertions manually, becoming a development bottleneck; missing assertions may lead to post-silicon security vulnerabilities with severe consequences. Although formal verification can mathematically prove design correctness, complex processor designs require thousands of assertions, taking months to write.

AutoAssert-RV is a research pipeline that uses LLMs to automatically generate hardware formal verification assertions, focusing on the hardware security domain. Its core idea is to leverage the code understanding and generation capabilities of LLMs to comprehend hardware description languages (such as Verilog/VHDL) and generate compliant assertions. The project repository includes key components: assertions/ (generated assertion library), docs/ (usage methods and technical details), jasper/ (integration code with JasperGold), pipeline/prompts/ (prompt engineering templates), and rtl/ (sample RTL files).

AutoAssert-RV workflow: Parse RTL designs to extract module interfaces, state machines, and other information → Organize into structured prompts for input to LLMs → After generating assertions, perform syntax checks, semantic validation, and redundancy elimination → Integrate with JasperGold for verification. The core technology is prompt engineering, which includes multi-level strategies: context construction (combining RTL semantics with natural language), security attribute guidance (specifying categories like confidentiality), and format constraints (few-shot examples to teach LLMs to output SVA syntax).

AutoAssert-RV has wide applications in the hardware security domain: quickly generating assertions for vulnerability patterns such as uninitialized sensitive registers and insecure debug interfaces; identifying edge cases overlooked by humans (e.g., information leakage caused by complex timing interactions); accelerating security audits (automatically generating candidate assertions for expert screening); and serving as an educational tool to help junior engineers understand assertion writing and security attribute expression.

Current limitations: Assertions generated by LLMs may have false positives/negatives requiring manual review; insufficient capture of semantics in complex designs; high computational resource requirements for verifying large designs. Future directions: Support more HDLs (e.g., Chisel, SpinalHDL); integrate verification tools like SymbiYosys; introduce reinforcement learning to optimize prompts and assertion selection; establish an open database of hardware security assertions to improve models.

AutoAssert-RV combines the language understanding capabilities of LLMs with the rigor of formal verification, providing new ideas for addressing the scalability challenges of hardware security verification. With the advancement of LLM technology and the growth of hardware security demands, such innovative tools will promote more efficient and accessible secure and reliable hardware design.