LLM-RTL-CI-Pipeline: An Automated Pipeline for RTL Design and Verification Based on Large Language Models

The LLM-RTL-CI-Pipeline project explores the application of large language models (LLMs) to the Register Transfer Level (RTL) design and verification processes of digital circuits. By building an automated CI/CD pipeline, it addresses the time-consuming and error-prone issues in traditional RTL development, with the goal of improving chip development efficiency and shortening time-to-market.

RTL is a key abstraction level in digital circuit design. The traditional process includes steps such as specification definition, RTL coding, functional verification, synthesis and implementation, timing analysis, and physical implementation. Among these, RTL coding and verification account for more than 70% of the chip development cycle, and the cost of fixing RTL code bugs in later stages grows exponentially, posing significant efficiency challenges.

LLMs can play multi-dimensional roles in RTL development:

• Code generation: Generate RTL code from natural language descriptions;
• Code completion: Intelligent completion to speed up the coding process;
• Code review: Check for compliance and potential bugs;
• Documentation generation: Maintain consistency between code and documentation;
• Test generation: Automatically generate testbenches and test cases;
• Error diagnosis: Analyze simulation failure logs and provide repair suggestions.

The core stages of the pipeline include:

1. Design input: Engineers describe design intent using natural language or structured formats;
2. LLM code generation: Convert design descriptions into RTL code, including architecture decomposition and interface definition;
3. Static analysis: Check syntax, style, synthesizability, and complexity;
4. Simulation verification: Automatically generate testbenches, test cases, and assertions, and execute regression tests;
5. Feedback iteration: Analyze failure causes, generate repair suggestions, and re-verify;
6. Delivery and release: Version tagging, documentation generation, and packaging for release to the repository.

Challenges and solutions for applying LLMs to RTL development:

• RTL professionalism: Fine-tune LLMs with RTL datasets or adopt RAG architecture;
• Correctness requirements: Establish a multi-level verification system (static analysis, formal verification, simulation);
• Synthesizability: Integrate tools like Yosys for rapid verification;
• Timing closure: Add timing analysis steps in the pipeline to evaluate critical paths.

The project can create value in multiple scenarios:

• Rapid prototyping: Generate runnable prototypes during architecture exploration;
• Standard modules: Generate common modules like FIFO and arbiters to reduce repetitive work;
• Code migration: Migrate legacy code across HDL languages or styles;
• Verification assistance: Automatically generate testbenches and assertions;
• Learning and training: Tools for new engineers to learn.

Current scenarios where LLMs cannot fully replace engineers: complex architecture design, PPA optimization, cross-module coordination, physical design considerations. Future directions:

• More professional training of RTL-specific models;
• Deep integration with EDA tools;
• Introduction of formal verification methods;
• Multimodal input (e.g., generating RTL from block diagrams);
• Automation of design space exploration.

LLM-RTL-CI-Pipeline is a cutting-edge exploration of AI-assisted chip design. Although it cannot fully automate RTL development, it can significantly improve efficiency in specific scenarios. As LLM capabilities enhance and the EDA ecosystem evolves, the human-machine collaboration model will become an industry standard. It is recommended that chip design teams explore and experiment with such automated pipelines to improve efficiency while maintaining quality.