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VeriAttn: A Communication-Efficient Verifiable Attention Mechanism for Large Language Model Inference

Addressing the performance bottleneck of large language model (LLM) inference under the protection of Trusted Execution Environment (TEE), VeriAttn offloads attention computation to the GPU and performs verification in the TEE. Combined with two-level pipeline optimization, it achieves 2.6-3.4x speedup in the prefill phase and 3.9-5.4x speedup in the decoding phase.

可信执行环境大语言模型推理注意力机制TEE-GPU协同计算完整性隐私计算Intel TDX可验证计算
Published 2026-06-15 15:50Recent activity 2026-06-16 10:55Estimated read 8 min
VeriAttn: A Communication-Efficient Verifiable Attention Mechanism for Large Language Model Inference
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Section 01

Introduction: VeriAttn—An Innovative Mechanism to Solve the Performance Bottleneck of TEE-Protected LLM Inference

Core Insights

To address the performance bottleneck of large language model (LLM) inference under the protection of Trusted Execution Environment (TEE), the research team proposes the VeriAttn mechanism: fully offload attention computation to the GPU, only verify the correctness of results in the TEE, and combine two-level pipeline optimization and intelligent partitioning strategy to achieve 2.60-3.38x speedup in the prefill phase and 3.86-5.42x speedup in the decoding phase.

Source Information

  • Original Title: Communication-Efficient Verifiable Attention for LLM Inference
  • Source Platform: arXiv
  • Publication Date: 2026-06-15
  • Original Link: http://arxiv.org/abs/2606.16352v1
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Section 02

Background: Performance Dilemma of TEE-Protected LLM Inference

Challenges of Trusted Inference

In cloud LLM deployment, computational integrity and data privacy protection are key issues. TEE provides a secure execution environment through hardware isolation, but directly applying existing solutions (such as TSDP) faces performance bottlenecks:

Analysis of Performance Bottlenecks

  1. TEE Computational Overhead: Security isolation leads to a significant slowdown in complex attention computation
  2. TEE-GPU Communication Overhead: KV cache transmission consumes a lot of bandwidth in long-sequence inference
  3. Special Nature of Attention Mechanism: The matrix operations and memory access patterns of Transformers are different from traditional DNNs, so direct application of TSDP is inefficient

Limitations of Existing Solutions

The TSDP scheme places nonlinear components in TEE, offloads linear components to GPU and verifies them, but it is not suitable for the attention mechanism of LLMs.

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Section 03

Methodology: Core Design Ideas of VeriAttn

Core Insight

Computation Offloading + Result Verification: Make full use of GPU computational efficiency and TEE security—fully offload attention computation to the GPU, and TEE only performs lightweight verification.

Full Offloading of Attention Computation

  • Linear Components: Query/Key/Value projection matrix operations
  • Nonlinear Components: Softmax normalization and attention weight computation After the GPU completes the computation, it returns the results to the TEE for verification, which are only used for subsequent computation after passing the verification.

TEE Lightweight Verification Mechanism

  • Result Check: Verify that the output meets mathematical constraints
  • Integrity Check: Ensure the computation has not been tampered with
  • Fast Rejection: Identify obviously incorrect results
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Section 04

Optimization Strategies: Performance Improvement in Prefill and Decoding Phases

Prefill Phase: Two-Level Pipeline Optimization

  • Architecture: Overlap data transmission, TEE preprocessing/postprocessing, and GPU computation for parallel execution
  • Benefits: 2.60-3.38x speedup under 6k token prompts, hiding transmission latency and fully utilizing GPU capabilities

Decoding Phase: Intelligent Partitioning Strategy

  • Partitioning Principle: Keep hot data (active KV) in GPU, store cold data (historical KV) in TEE/system memory
  • Memory Optimization: On-demand loading, cache prediction preloading, compressed transmission
  • Benefits: 3.86-5.42x speedup under 10k token outputs, reducing repeated KV transmission
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Section 05

Experimental Evaluation: Performance and Security Verification

Experimental Setup

  • Hardware: Intel TDX platform
  • Comparison Baseline: TSDP scheme
  • Scenarios: Prefill (6k tokens), Decoding (10k tokens)

Performance Results

Phase Speedup Key Optimization
Prefill 2.60-3.38x Two-level pipeline, computation offloading
Decoding 3.86-5.42x Intelligent partitioning, reduced KV transmission

Security Analysis

  • Computational Integrity: TEE verification ensures correct results
  • Data Confidentiality: Sensitive data is processed in TEE and not leaked to GPU
  • Tamper Resistance: Tampered results will be detected by TEE
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Section 06

Technical Contributions and Practical Value

Technical Contributions

  1. Paradigm Innovation: First application of "verification offloading" to the attention mechanism
  2. Pipeline Design: Two-level pipeline solves long-sequence inference latency
  3. Intelligent Partitioning: Memory and transmission optimization in the decoding phase

Practical Value

  • Privacy-Preserving Inference: Balances performance and data privacy
  • Compliance Deployment: Meets data protection regulations such as GDPR
  • Enterprise Applications: Supports cloud LLM inference for sensitive business data
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Section 07

Limitations and Future Work Directions

Limitations

  1. Hardware Dependency: Currently based on Intel TDX; porting to other TEEs (e.g., AMD SEV) requires additional work
  2. Verification Overhead: Although lightweight, there is still a certain burden
  3. Attack Resistance: Resistance to advanced side-channel attacks needs further research

Future Directions

  • Extend to other TEE platforms
  • Explore more efficient verification mechanisms
  • Apply to multimodal models and distributed inference scenarios