Implementing VLSI Intelligent Floorplanning with Reinforcement Learning + Graph Neural Networks: RL+GNN+PPO Chip Design Automation Solution

This project is an end-to-end VLSI physical design automation framework. Its core innovation lies in combining Graph Neural Networks (GNN) to extract circuit connection features and using the PPO reinforcement learning algorithm to learn optimal cell placement strategies, achieving collision-free and low wirelength intelligent chip floorplanning. The project is maintained by saikiran229, sourced from GitHub, released on 2026-05-27, original link: https://github.com/saikiran229/VLSI-AI-Floorplanning-using-RL-GNN-PPO.

Very Large Scale Integration (VLSI) physical design is one of the most complex stages in chip manufacturing. Traditional floorplanning and routing techniques rely on simulated annealing algorithms, heuristic optimization, and extensive manual parameter tuning. For modern chip netlists with millions of components, challenges include exponentially increasing computational costs, difficulty in global optimization, and long design cycles. The industry urgently needs intelligent automation solutions that optimize objectives such as wirelength, congestion, and timing while ensuring layout legality. The application of deep learning and reinforcement learning in the EDA field shows great potential.

Project Overview

Build a complete intelligent floorplanning framework, with the core being the combination of GNN and reinforcement learning:

1. Graph Representation Learning: Model the netlist as a graph (nodes = macro cells/standard cells, edges = signal connections);
2. GNN Feature Extraction: Use PyTorch Geometric to extract circuit structure features and connection patterns;
3. RL Decision-Making: PPO agent learns placement strategies in the Gymnasium environment;
4. Multi-Objective Optimization: Minimize Half-Perimeter Wirelength (HPWL), eliminate cell overlaps, and reduce congestion.

Technical Architecture

Core Components:

Module	Technology Selection	Function
Graph Learning	PyTorch Geometric	Extract node embeddings and structural features
RL	Stable-Baselines3 (PPO)	Learn placement strategies
Environment	Gymnasium	Interactive training environment
Layout Processing	Gdstk, KLayout	GDSII import/export
Visualization	Matplotlib, TensorBoard	Training monitoring and display

Data Flow: Netlist input → Graph construction → GNN feature extraction → Custom RL environment → PPO training → Floorplanning optimization → Visualization and GDSII export

Training Mechanism

• Environment Design: State space (cell positions, netlist structure, placed information); Action space (discrete placement positions); Termination conditions (all cells placed or illegal state).
• Reward Function: Composite strategy (penalize overlaps/illegal areas/long wires; reward compact layout/legal placement/HPWL reduction).

Training Scale

• Training steps: 200,704 timesteps
• Training speed: 49 FPS
• Platform: Ubuntu Linux (VirtualBox virtual machine)

Key Metrics

• Collision Elimination: Initial large number of overlaps → final collision score 0;
• Wirelength Optimization: Initial HPWL ~1100 → optimized to 598.5 (≈50% improvement);
• Optimal Legal Layout: Best legal HPWL is 114.

The results show that the trained PPO agent can stably generate legal and optimized floorplanning solutions.

This project demonstrates the practical application path of AI in the chip design field. Compared to industrial-grade solutions (e.g., Google Circuit Training), it uses a lightweight tech stack to validate core capabilities, making it suitable for academic research and rapid prototyping.

Key Insights:

1. Graph representation is a natural abstraction for circuit problems, and GNN effectively captures topological structures and connection patterns;
2. Reinforcement learning is suitable for combinatorial optimization, and the floorplanning decision sequence conforms to the MDP framework;
3. Reward engineering is crucial; composite rewards are more effective than single objectives in guiding valid strategies;
4. Modular architecture facilitates iteration, and clear layering makes problem localization and improvement easier.

Industry Significance: As chip complexity increases, AI-driven physical design automation will become an industry standard. Open-source projects provide valuable resources for technology popularization and talent cultivation.

Current Capabilities

• Process standard netlist formats;
• Generate visual floorplanning heatmaps;
• Export production-grade GDSII layout files;
• Validate results in professional tools like KLayout.

Future Expansion Directions

1. Multi-objective optimization: Consider timing, power consumption, area, etc., simultaneously;
2. Timing awareness: Incorporate critical path timing constraints into the reward function;
3. Congestion prediction: Integrate routing congestion estimation models;
4. Transformer encoding: Explore more advanced graph encoder architectures;
5. Hierarchical floorplanning: Support hierarchical processing of large-scale designs;
6. Distributed training: Use multi-GPU to accelerate strategy learning.