NeuroVHDL: Hardware Implementation of Artificial Neural Networks on FPGA and MNIST Handwritten Digit Recognition

NeuroVHDL is an open-source project that uses the VHDL language and Intel Quartus development environment to implement an artificial neural network for MNIST handwritten digit recognition on an FPGA architecture. This project demonstrates the complete migration process of neural networks from software to hardware, aiming to provide a reference implementation for FPGA-based neural network acceleration, suitable for edge computing and other scenarios with high requirements for real-time performance and energy efficiency.

With the development of AI technology, traditional CPUs/GPUs running neural networks face problems such as high power consumption, large latency, and insufficient real-time performance, which are particularly prominent in edge computing scenarios. As a reconfigurable hardware platform, FPGA has advantages such as strong parallel processing capability, low power consumption, and controllable latency, providing new possibilities for efficient deployment of neural networks. The NeuroVHDL project was born in this context, focusing on migrating artificial neural networks from software to FPGA hardware platforms.

Application of VHDL Language

VHDL is used to describe the hardware structure of the neural network (neurons, activation functions, weight storage, etc.), which is finally synthesized into logic gate circuits.

MLP Architecture Design

• Input Layer: Receives 28×28 pixels (784 nodes), with pixel values quantized into fixed-width integers.
• Hidden Layer: A fully connected layer, with the core being multiply-accumulate (MAC) operations, using fixed-point numbers to ensure resource efficiency.
• Output Layer: 10 neurons corresponding to 0-9 classification, with results determined by maximum value selection or Softmax.

Activation Function Implementation

ReLU is efficiently implemented via comparators; Sigmoid/Tanh require lookup tables or piecewise linear approximation to balance accuracy and resources.

Intel Quartus Development Flow

Includes steps such as design input, functional simulation, synthesis, placement and routing, timing analysis, and download configuration.

Introduction to MNIST Dataset

Contains 60,000 training images and 10,000 test images, 28×28 grayscale handwritten digits, which is a classic benchmark for machine learning.

Hardware Inference Steps

1. Image data is input into the FPGA via external interfaces (UART/SPI, etc.);
2. After preprocessing (normalization, quantization), it is sent to the input layer;
3. Parallel computation is performed at each layer, propagating layer by layer;
4. The output layer generates confidence levels for 10 classes, and the highest score is selected as the result;
5. The result is returned via the output interface. The entire process has a latency of microsecond level, which is much faster than software implementation.

Fixed-Point Quantization

Quantize weights and activation values into 8/16-bit fixed-point numbers (replacing floating-point numbers), implemented using DSP blocks or logic resources to reduce power consumption and area.

Parallel Computing Architecture

• Intra-layer parallelism: Multiple neurons in the same layer compute simultaneously;
• Inter-layer pipelining: Different layers form a pipeline to improve throughput;
• Vector parallelism: Parallel processing of input vectors. A trade-off between performance, resources, and power consumption is required.

Storage Optimization

• On-chip BRAM stores active parameters;
• Weight sharing/pruning reduces the number of parameters;
• Efficient data reuse reduces external storage access.

Edge Computing Devices

Suitable for scenarios sensitive to power consumption and latency, such as industrial quality inspection cameras, smart access control, and UAV vision modules.

Real-Time Signal Processing

Can be extended to tasks such as speech recognition, vibration analysis, and sensor data fusion.

Model Expansion

Although currently an MLP architecture, it can be extended to:

• Convolutional Neural Networks (CNN): Implement convolution kernels and pooling operations;
• Recurrent Neural Networks (RNN): Add state storage and feedback;
• Lightweight models: Edge-friendly architectures such as MobileNet and SqueezeNet.

Trade-off Between Accuracy and Resources

• Mixed-precision design: Use higher precision for key layers;
• Knowledge distillation: Train lightweight student networks;
• Extreme quantization: Binary/ternary neural networks.

Reducing Development Complexity

• High-Level Synthesis (HLS): Automatically generate hardware from C/C++;
• Reuse IP core libraries: Reduce repetitive development;
• Automatic conversion process: Seamless connection from training frameworks to hardware.

NeuroVHDL provides developers with a reference case for neural network hardware implementation, helping to understand the mapping from mathematical operations to hardware circuits and master key technologies such as fixed-point quantization and parallel architecture. In today's booming era of AI chips and edge computing, mastering neural network hardware implementation is an important skill for embedded and AI engineers, and NeuroVHDL is a good starting point to enter this field.