In-Sensor-Memory Computing (ISMC) Architecture: The Next-Generation Intelligent Computing Paradigm Breaking Through the von Neumann Bottleneck

The traditional von Neumann architecture suffers from the "memory wall" problem due to the separation of processor and memory; 90% of energy consumption in AI inference tasks is spent on data movement. The demand for edge computing is surging (scenarios like autonomous driving and industrial sensors require local real-time processing, while cloud computing faces bandwidth, latency, and privacy challenges). In-Sensor-Memory Computing (ISMC) technology integrates storage and computing, fundamentally reconstructing hardware architecture to achieve ultra-low power consumption and ultra-low latency edge intelligence, making it a key computing paradigm in the post-Moore era.

Inherent flaws of the von Neumann architecture: separation of processor and memory leads to the "memory wall", with data movement accounting for an extremely high proportion of energy consumption. The popularization of the Internet of Things (IoT) drives edge computing demand; scenarios like autonomous driving, industrial sensors, and smart cameras require computing to be offloaded to the data source, and cloud computing cannot meet the threefold challenges of bandwidth, latency, and privacy. ISMC technology emerged in this context.

Core concept: Perform computing where data is stored. Three technical paths: 1. Near-memory computing (CMOS process, integrating computing units next to storage); 2. In-memory computing (using new memory technologies like RRAM/PCM/FeRAM to perform matrix operations directly in storage cells); 3. In-sensor-memory computing (monolithic integration of sensors, storage, and computing). Key device: Memristor—its conductance can be precisely adjusted and retained after power-off; arrays naturally implement matrix-vector multiplication, and analog-domain computing eliminates the need for data movement.

Academia: Tsinghua University, Peking University, Stanford University, etc., have made breakthroughs in memristor process, array integration, and algorithm mapping. Industry: TSMC, Intel, Micron are laying out product lines, and startups have received financing. Maturity: NOR Flash-based ISMC chips have been mass-produced (for edge AI scenarios); RRAM solutions are expected to be commercialized in 2-3 years; new materials are expected to improve energy efficiency by 1-2 orders of magnitude. Architectural shift: From "processor-centric" to "data-centric". Integration with neuromorphic computing (SNN aligns with ISMC characteristics, enabling low-power processing of time-series data).

Smart security: Local face recognition/behavior analysis reduces bandwidth and privacy risks. Wearable devices: Real-time health monitoring (heart rate, blood oxygen, etc.) with low-power operation. Industrial IoT: Smart sensors perform real-time anomaly detection; predictive maintenance reduces downtime by over 30%. Autonomous driving: Perception fusion at the sensor end improves response speed.

Challenges: 1. Device reliability (memristor process fluctuations affect accuracy; circuit optimization and algorithm fault tolerance are needed); 2. Software ecosystem (specialized toolchains are required to lower development thresholds); 3. System integration (heterogeneous integration is complex; Chiplet/3D stacking is a viable path). Outlook: Together with quantum/optical computing, it will form the landscape of the post-Moore era; energy efficiency will be improved to the level of the human brain, enabling ubiquitous intelligent computing.

ISMC is a rethinking of the essence of computing, not incremental optimization; data does not need to be moved over long distances, and computing is integrated into storage. Implications for AI chip, edge computing, and intelligent application practitioners: Seizing the opportunity of this paradigm shift is an important future technology investment.