FPGA-Based Spiking Neural Network Accelerator: Hardware Implementation of Brain-Inspired MNIST Handwritten Digit Recognition

This project was developed by Dinesh-Vardhan and open-sourced on GitHub (Project link: https://github.com/Dinesh-Vardhan/FPGA-Based-Spiking-Neural-Network-MNIST, Release date: June 11, 2026). The core content is the implementation of a Spiking Neural Network (SNN) accelerator on FPGA using Verilog HDL, which adopts the LIF neuron model, STDP learning mechanism, and Winner-Take-All (WTA) competition mechanism to complete the MNIST handwritten digit recognition task, providing a practical open-source reference solution for edge AI and neuromorphic computing.

Traditional Deep Neural Networks (DNNs) face problems such as high power consumption, high latency, and memory dependency when deployed on resource-constrained edge devices. As a biologically inspired computing paradigm, neuromorphic computing and Spiking Neural Networks (SNNs) transmit information through event-driven discrete spikes, consuming energy only when neurons fire, thus having energy efficiency advantages. They also have time encoding capabilities, can naturally process temporal information, and are closer to biological nervous systems, providing a new direction for edge AI.

The project adopts a modular hardware design, with the data flow as follows: MNIST images are converted into spike sequences via a Poisson spike encoder (based on LFSR pseudo-random mechanism) → synaptic layer completes weight multiplication → LIF neuron array (integrates input current, simulates membrane potential decay and threshold triggering) → WTA mechanism selects the neuron with the highest activation as the recognition result. Core components include:

1. LIF neurons: Simulate the membrane potential dynamics of biological neurons, implemented via digital accumulators and comparators;
2. STDP learning: Adjust synaptic strength according to the relative time of spikes from pre- and post-neurons, complying with Hebbian rules;
3. WTA competition: Ensure a single neuron wins through lateral inhibition to avoid category ambiguity;
4. Adaptive threshold: Dynamically adjust neuron thresholds to prevent a single neuron from dominating.

Implemented in the Xilinx Vivado environment, optimized for FPGA characteristics:

1. Fixed-point arithmetic: Replaces floating-point arithmetic to reduce resource overhead while ensuring precision;
2. Parallel and pipeline design: Multiple LIF neurons work in parallel, and synaptic weights are stored in RAM to support parallel reading;
3. Event-driven architecture: Although FPGAs have high static power consumption, this lays the foundation for future ASIC implementation, where circuits are activated only when spikes are triggered, significantly improving energy efficiency.

Application Scenarios:

• Edge AI: Suitable for smart sensors, wearable devices, and industrial monitoring systems to achieve low-latency, low-power inference;
• Robotics: Provide perception and decision-making capabilities close to biological nervous systems for joint controllers, visual processing units, and navigation systems. Future Expansion:
• Introduce convolutional layers to handle complex visual tasks (e.g., CIFAR-10/ImageNet);
• Optimize storage and interconnection to support larger-scale neuron arrays;
• Establish a SystemVerilog verification environment;
• Build neuromorphic computing clusters by connecting multiple FPGAs via high-speed links.

This project verifies the feasibility of implementing biologically inspired neural networks on FPGAs using hardware description languages, providing an efficient solution for edge AI. The project provides complete source code, architecture diagrams, and waveform simulation results, making it a high-quality resource for learning neuromorphic computing, hardware acceleration, and edge AI. As neuromorphic chip technology matures, such architectures will play an important role in future intelligent systems.