Neural Networks on FPGA: Lightweight MLP Hardware Implementation for Edge Computing

This graduation project from the Department of Electronic Engineering at the University of Manchester focuses on implementing area-optimized Multi-Layer Perceptron (MLP) neural networks on FPGA hardware, aiming to solve the problem of AI deployment in resource-constrained edge device environments. The project deeply explores core content such as architectural design of neural network hardware acceleration, fixed-point quantization techniques, and resource optimization strategies, promoting the extension of intelligent computing to the source of data generation and providing important references for edge AI engineering practices.

Deep learning requires massive computation, and cloud-based inference has issues like privacy concerns, latency, and network dependency—thus edge AI emerged, which runs intelligent algorithms on resource-constrained devices. FPGAs have advantages such as deterministic latency (critical for real-time scenarios), high energy efficiency (power consumption is only 1/10 to 1/100 of GPUs), and flexibility (field-programmable, unlike ASICs with fixed functions), but they also have limitations like high development difficulty and complex toolchains. This project demonstrates the direction of embedded AI: pushing intelligence to the source of data generation.

The project adopts an area-first design philosophy, choosing a three-layer MLP structure (input layer, hidden layer, output layer). Approximation schemes for activation functions (such as storing precomputed values in LUTs or piecewise linear approximation) are used to reduce resource usage. Fixed-point quantization technology is employed to balance accuracy and resources: determining bit width and decimal point positions (e.g., INT16/INT8), using quantization-aware training (or post-training calibration) to adapt to low-precision representations, and using saturation/truncation strategies to handle overflow risks.

The hardware architecture uses a pipeline scheme with intra-layer parallelism and inter-layer serialism to balance resource efficiency and inference speed. Resource optimization includes weight sharing (reducing storage), operation fusion (eliminating redundancy), storage layout planning (reasonable allocation of BRAM and DRAM), and clock domain optimization (separating high-speed and low-speed modules). Development process: Python algorithm prototype → quantization simulation → HLS synthesis (C/C++ to RTL) → RTL implementation and hardware verification.

The solution is suitable for edge scenarios: industrial predictive maintenance (real-time anomaly detection), intelligent security cameras (local analysis), wearable health monitoring (low-power real-time signal analysis), and drone autonomous navigation (onboard AI). Performance evaluation dimensions: resource utilization (LUT/FF/BRAM/DSP consumption), inference latency (clock cycles and millisecond-level latency), power consumption (energy efficiency compared to GPUs), and accuracy retention (control of precision loss after quantization).

Project limitations: small network scale (only supports small-scale MLPs), limited architecture support (no CNN/Transformer). Future directions: sparsification technology (pruning to reduce parameters), adaptive precision (dynamically adjusting computation precision), multi-task learning (single hardware supporting multiple tasks), memristor integration (in-memory computing to break the von Neumann bottleneck). Conclusion: This project is an important exploration in edge AI engineering practice, laying the foundation for underlying technology innovation in everything intelligence.