VLSI Implementation of Spiking Neural Networks: A Complete Design Flow from Algorithm to Chip

This project is an undergraduate graduation design that demonstrates the complete flow of spiking neural network (SNN) implementation from algorithm design to VLSI physical realization, covering core steps such as network architecture design, Verilog RTL coding, FPGA verification, and ASIC physical implementation. It uses toolchains like Vivado and OpenLane, providing a practical reference case for neuromorphic computing chip development.

Spiking Neural Networks (SNNs) are the third generation of neural networks, simulating biological neurons that transmit information via spikes. Unlike traditional ANNs with continuous activation, SNNs process temporal information using discrete spike events. Their advantages include event-driven computing (high energy efficiency), temporal information processing (suitable for dynamic data), and neuromorphic compatibility (matching hardware like Loihi/TrueNorth). The goal of this project is to achieve end-to-end implementation of SNNs from algorithm to physical chip.

Toolchain: Uses Vivado 2024.2 (FPGA development), OpenLane (open-source ASIC flow), Magic VLSI (layout editing), KLayout (layout viewing). Design Hierarchy: Algorithm design → RTL coding → Functional simulation → FPGA verification → Logic synthesis → Physical design → Sign-off verification. The toolchain is mainly open-source, suitable for academic environments.

Neuron Model: Uses the classic LIF model, with principles including membrane potential integration, leak decay, threshold firing, and reset. Mathematical description: τ_mdV/dt = -(V-V_rest)+RI(t). Network Topology: Presumed to be a fully connected multi-layer feedforward structure, with input layer spike coding (rate/time) and output layer spike counting or first spike time coding. Hardware Considerations: Parallelism (simultaneous update of multiple neurons), storage requirements (on-chip storage of synaptic weights), precision trade-offs (affecting area and power consumption), timing control (global clock or asynchronous drive).

FPGA Verification: Completes RTL writing, functional simulation, synthesis optimization, bitstream generation, and FPGA hardware verification via Vivado. Advantages include fast iteration and observable internal signals. ASIC Physical Implementation: Uses the OpenLane flow:

1. Synthesis (Yosys converts RTL to gate-level netlist; target process library may be SkyWater 130nm);
2. Floorplanning (chip size, IO/power ring placement);
3. Placement (standard cell placement, optimizing timing and congestion);
4. Routing (metal layer wiring, meeting rules);
5. Physical verification (DRC, LVS, STA).

ADC Simulation: Includes full-range simulation, indicating that the system needs to convert analog signals into digital spike inputs, verifying ADC linearity and accuracy. Coding Scheme Comparison: Shows binary/thermometer coding schemes for 4-bit ADC, affecting circuit complexity and power consumption. Physical Layout: KLayout screenshots show standard cell arrangement, metal layer routing, IO layout, and chip utilization, serving as tangible evidence of the complete flow.

Educational Significance: Interdisciplinary integration (neuroscience, computer science, electronic engineering), full-flow experience, open-source tools lowering entry barriers. Technical Challenges and Solutions:

• Analog-digital mixed design: Digital approximation or mixed-signal design;
• Storage bandwidth: On-chip SRAM, weight sharing, or sparse connections;
• Timing synchronization: Global clock or asynchronous design. Comparison with Commercial Chips: Small scale (small verification chip), open-source 130nm process, possibly offline training, application scenario as teaching verification (compared to Loihi's 130k neurons and 14nm process, etc.).

Although this project has a limited scale, it covers core steps of digital chip design, providing a reference path for students learning VLSI and neuromorphic computing. Open-source toolchains lower the threshold for chip design. With the rise of AI chips and edge computing, compound engineers with end-to-end design capabilities will be more popular, and such projects have important value for talent cultivation.